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ir3508z page 1 of 19 jan 09, 2009 data sheet xphase3 tm phase ic description the ir3508z phase ic combined with any ir xphase3 tm control ic provides a full featured and flexible w ay to implement a power solution for the latest high p erformance cpus and asics. the ?control? ic provide s overall system control and interfaces with any numb er of ?phase? ics which each drive and monitor a si ngle phase of a multiphase converter. the xphase3 tm architecture results in a power supply that is sma ller, less expensive, and easier to design while providing hig her efficiency than conventional approaches. the ir3508z disables its current sense amplifiers w hen entering power savings mode. the recommended use for these phase ics is for applications without adaptive voltage positioning where two or more pow er stages will be operating in power savings mode. features ir3508z phase ic ? power state indicator (psi) interface provides the capability to maximize the efficiency at light loa ds. ? anti-bias circuitry ? 7v/2a gate drivers (4a gatel sink current) ? support converter output voltage up to 5.1 v (limi ted to vccl-1.4v) ? loss-less inductor current sensing ? phase delay dff bypassed during psi assertion mode to improve output ripple performance ? over-current protection during psi assertion mode operation ? feed-forward voltage mode control ? integrated boot-strap synchronous pfet ? only four external components per phase ? 3 wire analog bus connects control and phase ics ( vid, error amp, iout) ? 3 wire digital bus for accurate daisy-chain phase timing control without external components ? debugging function isolates phase ic from the conv erter ? self-calibration of pwm ramp, current sense amplif ier, and current share amplifier ? single-wire bidirectional average current sharing ? small thermally enhanced 20l 4 x 4mm mlpq package ? rohs compliant application circuit figure 1 application circuit
ir3508z page 2 of 19 jan 09, 2009 ordering information part number package order quantity ir3508zmtrpbf 20 lead mlpq (4 x 4 mm body) 3000 per reel * IR3508ZMPBF 20 lead mlpq (4 x 4 mm body) 100 piece strips * samples only absolute maximum ratings stresses beyond those listed under ?absolute maximu m ratings? may cause permanent damage to the device. these are stress ratings only and functiona l operation of the device, at these or any other conditions, beyond those indicated in the operation al sections of the specifications are not implied. operating junction temperature?????.. 0 to 150 o c storage temperature range???????.-65 o c to 150 o c msl rating???????????????2 reflow temperature???????????.260 o c note: 1. maximum gateh ? sw = 8v 2. maximum boost ? gateh = 8v pin # pin name v max v min i source i sink 1 iout 8v -0.3v 1ma 1ma 2 psi 8v -0.3v 1ma 1ma 3 dacin 3.3v -0.3v 1ma 1ma 4 lgnd n/a n/a n/a n/a 5 phsin 8v -0.3v 1ma 1ma 6 nc n/a n/a n/a n/a 7 phsout 8v -0.3v 2ma 2ma 8 clkin 8v -0.3v 1ma 1ma 9 pgnd 0.3v -0.3v 5a for 100ns, 200ma dc n/a 10 gatel 8v -0.3v dc, -5v for 100ns 5a for 100ns, 200ma dc 5a for 100ns, 200ma dc 11 nc n/a n/a n/a n/a 12 vccl 8v -0.3v n/a 5a for 100ns, 200ma dc 13 boost 40v -0.3v 1a for 100ns, 100ma dc 3a for 100ns, 100ma dc 14 gateh 40v -0.3v dc, -5v for 100ns 3a for 100ns, 100ma dc 3a for 100ns, 100ma dc 15 sw 34v -0.3v dc, -5v for 100ns 3a for 100ns, 100ma dc n/a 16 vcc 34v -0.3v n/a 10ma 17 csin+ 8v -0.3v 1ma 1ma 18 csin- 8v -0.3v 1ma 1ma 19 eain 8v -0.3v 1ma 1ma 20 nc n/a n/a n/a n/a
ir3508z page 3 of 19 jan 09, 2009 recommended operating conditions for reliable opera tion with margin 8.0v v cc 28v, 4.75v v ccl 7.5v, 0 o c t j 125 o c. 0.5v v(dacin) 1.6v, 500khz clkin 9mhz, 250khz phsin 1.5mhz. electrical characteristics the electrical characteristics table lists the para metric range guaranteed to be within the recommende d operating conditions. typical values represent the median val ues, which are related to 25c. c gateh = 3.3nf, c gatel = 6.8nf (unless otherwise specified) parameter test condition min typ max unit gate drivers gateh source resistance boost ? sw = 7v. note 1 1. 0 2.5 gateh sink resistance boost ? sw = 7v. note 1 1.0 2.5 gatel source resistance vccl ? pgnd = 7v. note 1 1 .0 2.5 gatel sink resistance vccl ? pgnd = 7v. note 1 0.4 1.0 gateh source current boost=7v, gateh=2.5v, sw=0v. 2.0 a gateh sink current boost=7v, gateh=2.5v, sw=0v. 2.0 a gatel source current vccl=7v, gatel=2.5v, pgnd=0v. 2.0 a gatel sink current vccl=7v, gatel=2.5v, pgnd=0v. 4.0 a gateh rise time boost ? sw = 7v, measure 1v to 4v transition time 5 10 ns gateh fall time boost ? sw = 7v, measure 4v to 1v transition time 5 10 ns gatel rise time vccl ? pgnd = 7v, measure 1v to 4v transition time 10 20 ns gatel fall time vccl ? pgnd = 7v, measure 4v to 1v transition time 5 10 ns gatel low to gateh high delay boost = vccl = 7v, sw = pgnd = 0v, measure time from gatel falling to 1v to gateh rising to 1v 10 20 40 ns gateh low to gatel high delay boost = vccl = 7v, sw = pgnd = 0v, measure time from gateh falling to 1v to gatel rising to 1v 10 20 40 ns disable pull-down resistance note 1 30 80 130 k clock clkin threshold compare to v(vccl) 40 45 57 % clkin bias current clkin = v(vccl) -0.5 0.0 0.5 a clkin phase delay measure time from clkin<1v to gat eh>1v 40 75 125 ns phsin threshold compare to v(vccl) 35 50 55 % phsout propagation delay measure time from clkin > (vccl * 50% ) to phsout > (vccl *50%). 10pf load @ 125 o c 4 15 35 ns phsin pull-down resistance 30 100 170 k phsout high voltage i(phsout) = -10ma, measure vccl ? phsout 1 0.6 v phsout low voltage i(phsout) = 10ma 0.4 1 v
ir3508z page 4 of 19 jan 09, 2009 parameter test condition min typ max unit pwm comparator pwm ramp slope vin=12v 42 52.5 57 mv/ %dc eain bias current 0 eain 3v -5 -0.3 5 a minimum pulse width note 1 55 70 ns current sense amplifier csin+/- bias current -200 0 200 na csin+/- bias current mismatch note 1 -50 0 50 na input offset voltage csin+ = csin- = dacin. measure input referred offset from dacin -1 0 1 mv gain 0.5v v(dacin) < 1.6v 30.0 32.5 35.0 v/v unity gain bandwidth c(iout)=10pf. measure at iout. note 1 4.8 6.8 8.8 mhz slew rate 6 v/ s differential input range 0.8v v(dacin) 1.6v, note 1 -10 50 mv differential input range 0.5v v(dacin) < 0.8v, note 1 -5 50 mv common mode input range note 1 0 note2 v rout at t j = 25 o c note 1 2.3 3.0 3.7 k rout at t j = 125 o c 3.6 4.7 5.4 k iout source current 0.5 1.6 2.9 ma iout sink current 0.5 1.4 2.9 ma share adjust amplifier input offset voltage note 1 -3 0 3 mv gain csin+ = csin- = dacin. note 1 4 5.0 6 v/v unity gain bandwidth note 1 4 8.5 17 khz pwm ramp floor voltage iout open, measure relative to dacin -116 0 116 mv maximum pwm ramp floor voltage iout = dacin ? 200mv. measure relative to floor voltage. 120 180 240 mv minimum pwm ramp floor voltage iout = dacin + 200mv. measure relative to floor voltage. -220 -160 -100 mv psi comparator rising threshold voltage note 1 520 620 700 mv falling threshold voltage note 1 400 550 650 mv hysteresis note 1 50 70 120 mv resistance 200 500 850 k floating voltage 800 1150 mv
ir3508z page 5 of 19 jan 09, 2009 note 1: guaranteed by design, but not tested in productio n note 2: v ccl -0.5v or v cc ? 2.5v, whichever is lower parameter test condition min typ max unit body brake comparator threshold voltage with eain decreasing measure relative to floor voltage -300 -200 -110 mv threshold voltage with eain increasing measure relative to floor voltage -200 -100 -10 mv hysteresis 70 105 130 mv propagation delay vccl = 5v. measure time from eain < v(dacin) (200mv overdrive) to gatel transition to < 4v. 40 65 90 ns ovp comparator ovp threshold step v(iout) up until gatel drives high. compare to v(vccl) -1.0 -0.8 -0.4 v propagation delay v(vccl)=5v, step v(iout) up from v(dacin) to v(vccl). measure time to v(gatel)>4v. 15 40 70 ns synchronous rectification disable comparator threshold voltage the ratio of v(csin-) / v(dacin), below which v(gatel) is always low. 66 75 86 % negative current comparator input offset voltage note1 -16 0 16 mv propagation delay time apply step voltage to v(csin +) ? v(csin-). measure time to v(gatel)< 1v. 100 200 400 ns bootstrap diode forward voltage i(boost) = 30ma, vccl = 6.8v 360 5 20 960 mv debug comparator threshold voltage compare to v(vccl) -250 -150 -50 mv general vcc supply current 8v v ( vcc) < 10v 1.1 4.0 6.1 ma vcc supply current 10v v ( vcc) 16v 1.1 2.0 4 ma vccl supply current 3.1 8.0 12.1 ma boost supply current 4.75v v ( boost)-v(sw ) 8v 0.5 1.5 3 ma dacin bias current -1.5 -0.75 1 a sw floating voltage 0.1 0.3 0.4 v
ir3508z page 6 of 19 jan 09, 2009 pin description pin# pin symbol pin description 1 iout output of the current sense amplifier is con nected to this pin through a 3k resistor. voltage on this pin is equal to v(dacin) + 33 [v(csin+) ? v(csin-)]. connecting all iout pins together creates a share b us which provides an indication of the average current being supplied by all the ph ases. the signal is used by the control ic for voltage positioning and over-current protection. ovp mode is initiated if the voltage on this pin rises above v(vccl)- 0.8 v. 2 psi logic low is an active low (i.e. low = low po wer state). 3 dacin reference voltage input from the control ic . the current sense signal and pwm ramp is referenced to the voltage on this pin. 4 lgnd ground for internal ic circuits. ic substrat e is connected to this pin. 5 phsin phase clock input. 6 nc no connection. 7 phsout phase clock output. 8 clkin clock input. 9 pgnd return for low side driver and reference for gateh non-overlap comparator. 10 gatel low-side driver output and input to gateh non-overlap comparator. 11 nc no connection. 12 vccl supply for low-side driver. internal bootst rap synchronous pfet is connected from this pin to the boost pin. 13 boost supply for high-side driver. internal boot strap synchronous pfet is connected between this pin and the vccl pin. 14 gateh high-side driver output and input to gatel non-overlap comparator. 15 sw return for high-side driver and reference for gatel non-overlap comparator. 16 vcc supply for internal ic circuits. 17 csin+ non-inverting input to the current sense a mplifier, and input to debug comparator. 18 csin- inverting input to the current sense ampli fier, and input to synchronous rectification disable comparator. 19 eain pwm comparator input from the error amplifi er output of control ic. body braking mode is initiated if the voltage on this pin is les s than v(dacin). 20 nc no connection.
ir3508z page 7 of 19 jan 09, 2009 system theory of operation system description the system consists of one control ic and a scalabl e array of phase converters, each requiring one pha se ic. the control ic communicates with the phase ics using th ree digital buses, i.e., clock, phsin, phsout and t hree analog buses, i.e., dac, ea, and iout. the digital buses a re responsible for switching frequency determinatio n and accurate phase timing control without any external component s. the analog buses are used for pwm control and cu rrent sharing between interleaved phases. the control ic incorpor ates all the system functions, i.e., vid, clock sig nals, error amplifier, fault protections, current monitor, etc. the phase ic implements the functions required by the converter of each phase, i.e., the gate drivers, pwm comparator and latch, over-voltage protection, phase disable c ircuit, current sensing and sharing, etc. pwm control method the pwm block diagram of the xphase3 tm architecture is shown in figure 1. feed-forward vo ltage mode control with trailing edge modulation is used. a high-gain and w ide-bandwidth voltage type error amplifier is imple mented in the controller?s design to achieve a fast voltage contr ol loop. input voltage is sensed by the phase ics t o provide feed- forward control. the feed-forward control compensat es the ramp slope based on the change in input volt age. the input voltage can change due to variations in the silver box output voltage or due to the wire and pcb-trace voltage drop related to changes in load current. pwm comparator rdrp1 off vsetpt clkin rcs ccs ishare phsin dacin vcc csin+ gatel eain gateh cbst vcch csin- sw pgnd vccl rthrm vid6 phsout vid6 rcomp off clk d q phsin psi ccomp off vid6 rfb + - vid6 + - + - + - + - clkin cdrp rcs + - +- ccs + - rdrp 3k gnd vout dacin vcc vdac vo lgnd iout phsin vosns- vosns+ gatel eain gateh iin vdrp vin fb eaout clkout csin- csin+ irosc vid6 vdac remote sense amplifier vcch cbst clk r d q q dffrh vccl gate drive voltage phsout pwm comparator vid6 vid6 psi vid6 clk d q + - + - + - + - + - 3k vid6 clk r d q q u248 dffrh vid6 + vid6 + - + body braking comparator ramp discharge clamp enable current sense amplifier rvsetpt pwm latch share adjust error amplifier reset dominant 1 2 phase ic pgnd vid6 psi - + sw vid6 + + - + thermal compensation enable ramp discharge clamp vdrp amp vdac body braking comparator vn ivsetpt clock generator pwm latch current sense amplifier imon error amplifier share adjust error amplifier reset dominant rfb1 cout control ic cfb 1 2 psi phase ic phsout off vid6 figure 1: pwm block diagram
ir3508z page 8 of 19 jan 09, 2009 frequency and phase timing control the oscillator is located in the control ic and the system clock frequency is programmable from 250khz to 9mhz by an external resistor. the control ic system clock sign al (clkout) is connected to clkin of all the phase ics. the phase timing of the phase ics is controlled by the daisy chain loop, where the control ic phase clock output (phsout) is connected to the phase clock input (phsin) of the f irst phase ic, and phsout of the first phase ic is connected to phsin of the second phase ic, etc. the last phase ic is connected back to phsin of the control ic to complete the daisy chain loop. during power up, the control ic s ends out clock signals from both clkout and phsout pins and detects the feedback at phsin pin to determine the phase number and monitor any fault in the daisy cha in loop. when the psi is asserted (active low), the phases are ef fectively removed from the daisy chain loop. figure 2 shows the phase timing for a four phase converter. the switch ing frequency is set by the resistor rosc. the cloc k frequency equals the number of phase times the switching freq uency. phase ic1 pwm latch set control ic clkout (phase ic clkin) control ic phsout (phase ic1 phsin) phase ic 1 phsout (phase ic2 phsin) phase ic 2 phsout (phase ic3 phsin) phase ic 3 phsout (phase ic4 phsin) phase ic4 phsout (control ic phsin) figure 2: four phase oscillator waveforms pwm operation the pwm comparator is located in the phase ic. upon receiving the falling edge of a clock pulse, the p wm latch is set and the pwm ramp voltage begins to increase. in ad dition, the low side driver is turned off and the h igh side driver is turned on after the non-overlap time expires (gatel < 1v). when the pwm ramp voltage exceeds the error amplifier?s output voltage, the pwm latch is reset and the inte rnal ramp capacitor is quickly discharged to the ou tput of the share adjust amplifier and remains discharged until the n ext clock pulse. this reset latch additionally turn s off the high side driver and enables the low side driver after the no n-overlap time concludes (switch node < 1v). the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nano seconds in response to a load step decrease. phases can overla p and go up to 100% duty cycle in response to a loa d step increase with turn-on gated by the clock pulses. an error amplifier output voltage greater than the co mmon mode input range, of the pwm comparator, results in 100% duty cycle regardless of the voltage of the pwm ramp. th is arrangement guarantees that the error amplifier is always in control and can demand 0 to 100% duty cyc le as required. it also favors response to a load step decrease, wh ich is appropriate, given that the low output to in put voltage ratio of most systems. the inductor current will increase mu ch more rapidly than decrease in response to load t ransients. this control method is designed to provide ?single cycle transient response.? the inductor current wil l change in response to load transients within a single switchi ng cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. an additional advantage of the architecture is that differences in ground or input voltage, at the phases, have no effect on operation since the pwm ramps are referenced to vda c. figure 3 depicts pwm operating waveforms under vari ous conditions.
ir3508z page 9 of 19 jan 09, 2009 phase ic clock pulse eain vdac pwmrmp gateh gatel steady-state operation duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase steady-state operation duty cycle decrease due to load decrease (body braking) or fault (vccluv, ocp, vid=11111x) figure 3: pwm operating waveforms body braking tm in a conventional synchronous buck converter, the m inimum time required to reduce the current in the i nductor in response to a load step decrease is; o min max slew v i i l t ) (* ? = the slew rate of the inductor current can be signif icantly increased by turning off the synchronous re ctifier in response to a load step decrease. the switch node voltage is then forced to decrease until conduction of the sy nchronous rectifier?s body diode occurs. this increases the v oltage across the inductor from vout to vout + v bodydiode . the minimum time required to reduce the current in the inductor in response to a load transient decrease i s now; bodydiode o min max slew v v i i l t + ? = ) (* since the voltage drop in the body diode is often c omparable to the output voltage, the inductor curre nt slew rate can be increased significantly. this patented technique is referred to as ?body braking? and is accomplished through the ?body braking comparator? located in the phase ic. if the error amplifier?s output voltage drops below the o utput voltage of the share adjust amplifier in the phase ic, this compar ator turns off the low side gate driver. lossless average inductor current sensing inductor current can be sensed by connecting a seri es resistor and a capacitor network in parallel wit h the inductor and measuring the voltage across the capacitor, as show n in figure 4. the equation of the sensing network is, cs cs l l cs cs l c c sr sl r s i c sr s v s v + + = + = 1 ) ( 1 1 ) ( ) (
ir3508z page 10 of 19 jan 09, 2009 usually the resistor rcs and capacitor ccs are chos en so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current t hrough l, and the sense circuit can be treated as i f only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component of the ind uctor current. figure 4: inductor current sensing and current sens e amplifier the advantage of sensing the inductor current versu s high side or low side sensing is that actual outp ut current being delivered to the load is obtained rather than peak or sampled information about the switch currents. t he output voltage can be positioned to meet a load line based on real time information. except for a sense resistor in s eries with the inductor, this is the only sense method that can su pport a single cycle transient response. other meth ods provide no information during either load increase (low side s ensing) or load decrease (high side sensing). an additional problem associated with peak or valle y current mode control for voltage positioning is t hat they suffer from peak-to-average errors. these errors will show in m any ways but one example is the effect of frequency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and th e output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensation, input voltage, and ou tput voltage are all additional sources of peak-to- average errors. current sense amplifier a high speed differential current sense amplifier i s located in the phase ic, as shown in figure 4. it s gain is nominally 32.5, and the 3850 ppm/oc increase in inductor dcr should be compensated in the voltage loop feedback path. the current sense amplifier can accept positive dif ferential input up to 50mv and negative up to -10mv before clipping. the output of the current sense amplifier is summed with the dac voltage and sent to the control ic an d other phases through an on-chip 3k resistor connected to the iout pin. the iout pins of all the phases are tied together and the voltage on the share bus represents the average cur rent through all the inductors and is used by the c ontrol ic for voltage positioning and current limit protection. t he input offset of this amplifier is calibrated to +/- 1mv in order to reduce the current sense error. the input offset voltage is the primary source of e rror for the current share loop. in order to achiev e very small input offset error and superior current sharing performan ce, the current sense amplifier continuously calibr ates itself. this calibration algorithm creates ripple on iout bus wi th a frequency of f sw /896 in a multiphase architecture. average current share loop current sharing between phases of the converter is achieved by the average current share loop in each phase ic. the output of the current sense amplifier is compared w ith the average current at the share bus. if curren t in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the pwm ramp thereby increasing its duty cycle and output c urrent; if current in a phase is larger than the av erage current, the share adjust amplifier of the phase will pull up th e starting point of the pwm ramp thereby decreasing its duty cycle and output current. the current share amplifier is inte rnally compensated so that the crossover frequency of the current c o l r l r cs c cs v o current sense amp csout i l v l v cs c
ir3508z page 11 of 19 jan 09, 2009 share loop is much slower than that of the voltage loop and the two loops do not interact. for proper current sharing the output of current sense amplifier should not exceed (vccl-1.4v) under all operating condition. ir3508z theory of operation block diagram the block diagram of the ir3508z is shown in figure 5, and specific features are discussed in the foll owing sections. + - + - clk d q + - + - + - vcc s r q eain + - + - lgnd iout gatel pgnd boost gateh csin+ vccl csin- phsin clkin dacin phsout sw rmpout pwm reset vcc calibration calibration dacin calibration csaout debug off share_adj phsin dacin dacin-share_adj vccl irosc irosc current sense amplifier body braking comparator pwm comparator pwm latch share adjust amplifier - 1v x32.5 + ovp comparator gatel non- overlap comparator 1v synchronous rectification disable comparator + pwm ramp generator gatel non- overlap latch gateh non- overlap latch gatel driver gateh driver set dominant x 0.75 debug comparator set dominant 0.8v (low=open) reset dominant 0.15v gateh non- overlap comparator negative current comparator 100mv pwmq 200mv (clkin for 1-phase) clk r d q vccl phsin . . . psi_sy nc clk r d q clk r d q q u183 dffrsh . . . . . clk d q psi_sy nc phase delay dff 8clk eain vccl 500k anti-bias latch + - psi 510mv 610mv clk d q r 1v reset dominant + psi comparator s r q negative current latch vccl eain 3k + - s r q + - + - psi_sync pwm_clk psi_sy nc figure 5: block diagram tri-state gate drivers the gate drivers are design to provide a 2a source and sink peak current (bottom gate driver can sink 4a). an adaptive non-overlap circuit monitors the voltage o n the gateh and gatel pins to prevent mosfet shoot- through current and minimizing body diode conductio n. the non-overlap latch is added to eliminate erro neous triggering caused by the switching noise. a fault c ondition is communicated to the phase ic via the co ntrol ic?s error amplifier without an additional dedicated signal li ne. the error amplifier?s output is driven low in r esponse to any fault condition detected by the controller, such as vccl under voltage or output overload, disabling t he phase ic and activating body braking tm . the ir3508z body braking tm comparator detects the low signal at the eain and drives the bottom gate output low. this tri-state o peration prevents negative inductor current and neg ative output voltage during power-down.
ir3508z page 12 of 19 jan 09, 2009 a synchronous rectification disable comparator is u sed to detect the converter?s csin- pin voltage, wh ich represents local converter output voltage. if the v oltage is below 75% of vdac and negative current is detected, gatel is driven low, which disables synchronous rec tification and eliminates negative current during p ower-up. the gate drivers are pulled low if the supply volta ge falls below the normal operating range. an 80k resistor is connected across the gateh/gatel and pgnd pins to p revent the gateh/gatel voltage from rising due to leakage or other causes under these conditions. pwm ramp every time the phase ic is powered up, the pwm ramp magnitude is calibrated to generate a 52.5 mv/% ra mp (vcc=12v). for example, a 15 % duty ratio will gen erate a ramp amplitude of 787.5 mv (15 x 52.5 mv) w ith 12v supply applied to vcc. feed-forward control is ach ieved by varying the pwm ramp proportionally with v cc voltage after calibration. power state indicator (psi) function from a system perspective, the psi input is control led by the system and is forced low when the load c urrent is lower than a preset limit and forced high when load current is higher than the preset limit. ir3508z can accept an active low signal on its psi input and force the dr ivers into tri-state, effectively, forcing the phas e ic into an off state. a psi-assert signal activates three features in the phase ic. first, it disconnects the iout pi n from the ishare bus (from a system perspective). ishare is u sed to report current and is used for over-current protection. by disconnecting the disabled phase fro m the ishare bus, proper current reporting and over -current protection level are ensured. secondly, the d flip -flop (dff) is disabled, bypassing the phase ic fro m the daisy chain loop. by removing the dff from the daisy chai n, the system ensures that proper phase delay is ac tivated among the active phases. finally, the gate drivers are forced to tri-state, disabling the phase ic fro m the power stage. figure 6 shows the impact of psi-assert on t he gate drivers. after an 8 cycle phsin delay follo wed by a clk falling edge, the psi_sync goes from 0 to 1. th is disables the gate drives and the dff. psi_sync psi 8 phsin delay d_pwm latch clk figure 6: psi assertion. debugging mode if the csin+ pin is pulled up to vccl voltage, ir35 08z enters into debugging mode. both drivers are pu lled low and iout output is disconnected from the current sh are bus, which isolates this phase ic from other ph ases. however, the phase timing from phsin to phsout does not change .
ir3508z page 13 of 19 jan 09, 2009 emulated bootstrap diode ir3508z integrates a pfet to emulate the bootstrap diode. if two or more top mosfets are to be driven at higher switching frequency, an external bootstrap diode co nnected from vccl pin to boost pin may be needed. over voltage protection (ovp) the ir3508z includes over-voltage protection that t urns on the low side mosfet to protect the load in the event of a shorted high-side mosfet, converter out of regula tion, or connection of the converter output to an e xcessive output voltage. as shown in figure 7, if iout pin v oltage is above v(vccl) ? 0.8v, which represents ov er-voltage condition detected by control ic, the over-voltage latch is set. gatel drives high and gateh drives lo w. the ovp circuit overrides the normal pwm operation and with in approximately 150ns will fully turn-on the low s ide mosfet, which remains in conduction until iout drops below v(vccl) ? 0.8v when over voltage ends. the over vol tage fault is latched in control ic and can only be rese t by cycling the power to control ic. the error amp lifier output (eain) is pulled down by control ic and will remain low. the lower mosfets alone can not clamp the out put voltage however a scr or n-mosfet could be triggere d with the ovp output to prevent processor damage. after ovp fault latch 130mv output voltage (vo) ovp threshold vccl-800 mv ovp condition normal operation iout(ishare) gatel (phase ic) gateh (phase ic) vdac error amplifier output (eaout) figure 7: over-voltage protection waveforms operation at higher output voltage the proper operation of the phase ic is ensured for output voltage up to 5.1v. similarly, the minimum vcc for proper operation of the phase ic is 8 v. operating below this minimum voltage, the current sharing per formance of the phase ic is affected.
ir3508z page 14 of 19 jan 09, 2009 design procedures - ir3508z inductor current sensing capacitor c cs and resistor r cs the dc resistance of the inductor is utilized to se nse the inductor current. usually the resistor r cs and capacitor c cs in parallel with the inductor are chosen to match t he time constant of the inductor, and therefore the voltage across the capacitor c cs represents the inductor current. if the two time c onstants are not the same, the ac component of the capacitor voltage is different from that of the real inductor current. the time constant mismatch does not affect the average current sharing among the multiple phases, but does affect the current signal iout as well as the output voltage during a load current transient if adaptive voltage positioning is being implemented. measure the inductance l and the inductor dc resist ance r l . pre-select the capacitor c cs and calculate r cs as follows. cs l cs c r l r = (1) bootstrap capacitor c bst depending on the duty cycle and gate drive current of the phase ic, a capacitor in the range of 0.1uf to 1uf is needed for the bootstrap circuit. decoupling capacitors for phase ic a 0.1uf-1uf decoupling capacitor is required at the vccl pin. current share loop compensation the internal compensation of current share loop ens ures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loop so t hat the interaction between the two loops is elimin ated. the crossover frequency of current share loop is approximately 8 khz.
ir3508z page 15 of 19 jan 09, 2009 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of t he pcb layout; therefore, minimizing the noise coupled to the ic. ? dedicate at least one middle layer for a ground pl ane, which is then split into signal ground plane ( lgnd) and power ground plane (pgnd). ? separate analog bus (eain, dacin, and iout) from d igital bus (clkin, psi, phsin, and phsout) to reduc e the noise coupling. ? connect pgnd to lgnd pins of each phase ic to the ground tab, which is tied to lgnd and pgnd planes respectively through vias. ? place current sense resistors and capacitors (r cs and c cs ) close to phase ic. use kelvin connection for the inductor current sense wires, but separate the two wires by ground polygon. the wire from the inductor terminal to csin- should not cross over the fast tr ansition nodes, i.e., switching nodes, gate drive o utputs, and bootstrap nodes. ? place the decoupling capacitors c vcc and c vccl as close as possible to vcc and vccl pins of the p hase ic respectively. ? place the phase ic as close as possible to the mos fets to reduce the parasitic resistance and inducta nce of the gate drive paths. ? place the input ceramic capacitors close to the dr ain of top mosfet and the source of bottom mosfet. use combination of different packages of ceramic capaci tors. ? there are two switching power loops. one loop incl udes the input capacitors, top mosfet, inductor, ou tput capacitors and the load; another loop consists of b ottom mosfet, inductor, output capacitors and the l oad. route the switching power paths using wide and shor t traces or polygons; use multiple vias for connect ions between layers. csin - clkin pgnd plane lgnd plane ground polygon pgnd gatel r cs vcc eain to digital bus to inductor sense to lgnd plane to vin to gate drive voltage phsin dacin psi phsout to top mosfet pgnd plane lgnd plane ground polygon to bottom mosfet to analog bus to switching node csin+ nc iout sw gateh lgnd boost vccl nc nc c cs c vccl c bst d bst
ir3508z page 16 of 19 jan 09, 2009 pcb metal and component placement ? lead land width should be equal to nominal part le ad width. the minimum lead to lead spacing should be 0.2mm to minimize shorting. ? lead land length should be equal to maximum part l ead length + 0.3 mm outboard extension + 0.05mm inboard extension. the outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment an d ensure a fillet. ? center pad land length and width should be equal t o maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) ? four 0.3mm diameter vias shall be placed in the pa d land spaced at 1.2mm, and connected to ground to minimize the noise effect on the ic and to transfer heat to the pcb. ? no pcb traces should be routed nor vias placed und er any of the 4 corners of the ic package. doing s o can cause the ic to rise up from the pcb resulting in p oor solder joints to the ic leads.
ir3508z page 17 of 19 jan 09, 2009 solder resist ? the solder resist should be pulled away from the m etal lead lands and center pad by a minimum of 0.06 mm. the solder resist mis-alignment is a maximum of 0.0 5mm and it is recommended that the lead lands are a ll non solder mask defined (nsmd). therefore, pulling the s/r 0.06mm will always ensure nsmd pads. ? the minimum solder resist width is 0.13mm. at the inside corner of the solder resist where the lead l and groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. ? ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lea d lands from the pad land. ? the 4 vias in the land pad should be tented with s older resist 0.4mm diameter, or 0.1mm larger than t he diameter of the via.
ir3508z page 18 of 19 jan 09, 2009 stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimi ze the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain re peatable solder release. ? the stencil lead land apertures should therefore b e shortened in length by 80% and centered on the le ad land. ? the land pad aperture should be striped with 0.25m m wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. ? the maximum length and width of the land pad stenc il aperture should be equal to the solder resist op ening minus an annular 0.2mm pull back to decrease the in cidence of shorting the center land to the lead lan ds when the part is pushed into the solder paste.
ir3508z page 19 of 19 jan 09, 2009 package information 20l mlpq (4 x 4 mm body) ? ja = 32 o c/w, jc = 3 o c/w data and specifications subject to change without n otice. this product has been designed and qualified for th e consumer market. qualification standards can be found on ir?s web si te. ir world headquarters: 233 kansas st., el segundo, california 90245, usa t el: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact informati on .

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